1. Technical Field of the Invention
The present invention generally relates to the field of integrated circuit memories and, more particularly, integrated circuit memories having an architecture with segmented writing lines. The invention is typically, but not exclusively, applied to random access magnetic memories of the MRAM type having such an architecture.
2. Description of Related Art
The following description of the invention refers to a MRAM type memory; some reminders of its operation are given below.
MRAM (Magnetic Random Access Memories) are memories of the non-volatile type, where each memory cell is formed by a magnetic tunnel junction. This type of memory has all the combined advantages of present existing semiconductor memories: speed both of writing and of reading, low consumption, non-volatility, and insensitivity to radiations. These advantages are moreover combined with an increased possibility of integration due to the small size of the cells.
A magnetic random access memory typically comprises a matrix of memory cells disposed in rows and columns, across which are passed metallic tracks dedicated to writing and reading. The metallic writing tracks extending along the rows of memory cells are termed writing word lines, and the metallic tracks extending along the columns of cells are termed writing bit lines. Each memory cell so placed at the intersection of a word line and a bit line stores one bit of information in the form of magnetic orientation.
In the standard architecture, the addressing of memory cells for writing then takes place using magnetic fields induced by a matrix network of metallic lines subjected to current pulses; only the memory cell at the intersection of the two selected writing lines having to turn over. For reading, a low amplitude current is sent via a reading bit line and a CMOS control transistor, for example, to read the resistance of the junction. It is to be noted that in this type of memory the reading circuitry is at least partially dissociated from the writing circuitry.
Each of the memory cells is in fact constituted by two magnetic layers, separated by an electrical layer. Each magnetic layer has its own magnetic orientation. The magnetic orientation of one of the layers, termed free layer, may be modified, while the magnetic orientation of the other layer, termed fixed layer, is fixed in a particular orientation. The magnetic orientations of the two layers may occur in two situations: either parallel, that is, aligned in the same direction, or antiparallel, that is, aligned in opposite directions. These two directions, parallel and antiparallel, represent the logic values 1 and 0 respectively. As an alternative, the parallel state may be interpreted as logic 0 and the antiparallel state as logic 1.
Writing therefore consists, for such a memory cell, of positioning the magnetic orientation in the free layer as a function of the desired logic state, in a state either parallel or antiparallel with respect to the magnetic orientation of the fixed layer.
External magnetic fields are typically applied to a selected cell to turn over the magnetic orientation in the free layer of this cell from one state to another. To do this, a writing current is applied respectively to the word line and the bit line intersecting at the location of the selected memory cell. The writing currents applied in this way to the selected word line and bit line create magnetic fields which, when they are combined at the intersection of the word line and the bit line, create magnetic fields which enable the magnetic orientation of the free layer of the selected memory cell to be switched from the parallel to the antiparallel state, or vice versa, as a function of the datum which is to be written in the cell.
The switching from one state to another of a selected memory cell while writing requires high magnetic fields for which sufficiently high currents have to be circulated, of the order of tens of milliamps, at the level of the magnetic tracks constituting the word and writing bit lines at whose intersection the selected memory cell for writing is located.
Moreover, the conductive tracks constituting the writing lines are resistive in nature. The fact or passing a high current of the order of tens of milliamps over a writing line will therefore inevitably cause a fall of potential at its terminals, by Ohm's law. A relatively high supply voltage is therefore necessary at the level of the writing control circuits, to compensate for the fall of potential through metallic writing lines.
However, future memory topologies, particularly responding to increasing constraints of integration, will prevent the use of high voltage transistors for writing current control circuits. In this perspective, convergence to a single nominal supply voltage, for example 1.2 volts, is therefore more and more sought after.
In this context, a MRAM memory architecture may be envisaged with segmented writing word and/or bit lines. In fact, in such an architecture, such as for example described in the patent document U.S. Pat. No. 6,594,191 (the disclosure of which is hereby incorporated by reference), the plural memory cells are disposed in segments along the memory plane. The writing bit and/or word lines crossing the memory plane are then themselves segmented, creating shorter writing current paths. This architecture then implies an equivalent resistive load of the weakest writing lines, thus allowing a lower nominal supply voltage because the line losses are smaller. Such a segmented writing line architecture also enables minimizing the probability of erroneous turnover of non-selected memory cells when writing. In fact, only the memory cells on the path of the selected line segment when writing will then be subjected to the magnetic field generated by passing the writing current through the segment, instead of the whole row and/or column of memory cells.
However, the installation of such an architecture with segmented writing word and/or bit lines implies a certain number of constraints, mainly bearing on the addressing of the different writing line segments.
To illustrate this statement, reference is made to FIG. 1, describing in a simplified manner a portion of an MRAM type memory plane according to a matrix architecture of segmented writing bit lines. A memory plane of the type considered then comprises plural segmented writing bit lines organized in a matrix according to a column architecture, typically 64, 128 or 256 lines, at whose intersection are located the MRAM type memory cells. To simplify the explanation, only two columns and two rows of memory cells have been shown.
Therefore only two writing bit line segments 10 and 20, extending along two columns of the memory plane, are shown with their associated writing circuitry. Two memory cells 30 and 40 are disposed at the intersection of a writing word line 50 and each of the writing bit line segments 10 and 20. An architecture furthermore comprising segmented writing word lines could also be envisaged. The writing circuitry associated with the writing bit line segments to be described could similarly be found at the level of the word line segments.
First of all, the writing bit line segments 10 and 20 are connected at one end to a supply 60, for example 1.2 volts. For writing addressing of one column among a plurality, column address decoding means are provided. These means are constituted by an address bus 70, carrying for example six column address signals in the case of a memory plane comprising 64 columns, associated with address decoding circuits 80 for each column, realized in static logic. The output of each column decoding circuit 80 is provide for piloting programming means 90 associated with the addressed writing bit line segment. These programming means 90, also ensuring the switching of the line segment to earth, are symbolically represented by a transistor of which the source is connected to an earth (ground) line 100, the drain is connected to the writing line segment 10 and the gate is controlled by the output of the column decoding circuit 80.
As for the reading circuitry, it is partially dissociated from the writing circuitry, and will be considered in more detail later in the description.
At this stage, it is suitable first of all to note that plural writing bit line segments (not shown) such as the segment 10, are cascaded along each column of the memory plane. For each cascaded segment of writing bit line, it is necessary to provide programming means, and associated address decoding means therefore have to be provided.
The major of disadvantage of such an architecture with segmented writing lines therefore resides in the necessary redundancy of the address decoding means at each occurrence of a writing line segment, so as to be able to select one writing segment among the plural segments.
In the perspective of a segmented architecture, and taking account of design requirements for increased density of the memories, reproducing the specific address decoding logic cannot be hoped for at the level of all the writing line segments, these elements in fact consuming much space on the memory plane.
There is accordingly a need to remedy the abovementioned disadvantages. It is proposed that a memory device include segmented writing lines in which addressing different writing line segments for writing does not lead to an overload of line address decoding means, and which does not penalize in terms of memory plane density.